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LTC692/LTC693 Microprocessor Supervisory Circuits
FEATURES
s s s s
DESCRIPTIO
(R)
s s s
s s s
s s s
UL Recognized (R) Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max.) On-Board Gating of RAM Chip Enable Signals SO8 and SO16 Packaging 4.40V Precision Voltage Monitor Power OK/Reset Time Delay: 200ms or Adjustable Minimum External Component Count 1A Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature Superior Upgrade for MAX690 Family
The LTC692/LTC693 provide complete power supply monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the Chip Enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V. The LTC692/LTC693 power the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC692/LTC963 provide an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period.
APPLICATI
s s s s
S
Critical P Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems
TYPICAL APPLICATI
VIN 7.5V LT1086-5 VIN ADJ VOUT 5V
10F
100F
0.1F
LTC692 LTC693 VBATT
0.1F
P SYSTEM P RESET P NMI I/O LINE
LTC692/3 * TA01
RESET OUTPUT VOLTAGE (V)
+
+
VCC
VOUT
POWER TO P CMOS RAM POWER
3V 51k PFI 10k MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS. GND RESET PFO WDI 0.1F
100
U
RESET Output Voltage vs Supply Voltage
5 TA = 25C EXTERNAL PULL-UP = 10A VBATT = 0V 4 3 2 1 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5
LTC692/3 * TA02
UO
UO
1
LTC692/LTC693 ABSOLUTE AXI U RATI GS (Notes 1 and 2)
VOUT Output Current .................. Short Circuit Protected Power Dissipation............................................. 500mW Operating Temperature Range LTC692C/LTC693C ............................... 0C to 70C LTC692I/LTC693I ............................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
Terminal Voltage VCC .................................................... - 0.3V to 6.0V VBATT ................................................. - 0.3V to 6.0V All Other Inputs .................. - 0.3V to (VOUT + 0.3V) Input Current VCC .............................................................. 200mA VBATT ............................................................. 50mA GND............................................................... 20mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VOUT 1 VCC 2 GND 3 PFI 4 N8 PACKAGE 8-LEAD PLASTIC DIP 8 7 6 5 VBATT RESET WDI PFO
ORDER PART NUMBER LTC692CN8 LTC692IN8 LTC692CS8 LTC692IS8 S8 PART MARKING 692 692I
S8 PACKAGE 8-LEAD PLASTIC SOIC
TJMAX = 110C, JA = 130C/W (N) TJMAX = 110C, JA = 180C/W (S) S8 Package Conditions: PCB Mount on FR4 Material, Still Air at 25C, Copper Trace
PRODUCT SELECTIO GUIDE
PINS LTC692 LTC693 LTC690 LTC691 LTC694 LTC695 LTC699 LTC1232 LTC1235 LTC694-3.3 LTC695-3.3 8 16 8 16 8 16 8 8 16 8 16 RESET THRESHOLD (V) 4.40 4.40 4.65 4.65 4.65 4.65 4.65 4.37/4.62 4.65 2.90 2.90 WATCHDOG TIMER X X X X X X X X X X X X X X X X X X X X X X BATTERY BACKUP X X X X X X POWER FAIL WARNING X X X X X X X X X RAM WRITE PROTECT PUSHBUTTON RESET CONDITIONAL BATTERY BACKUP
2
U
U
W
WW
U
U
W
(Note 3)
TOP VIEW VBATT VOUT VCC GND BATT ON LOW LINE OSC IN OSC SEL 1 2 3 4 5 6 7 8 16 RESET 15 RESET 14 WDO 13 CE IN 12 CE OUT 11 WDI 10 PFO 9 PFI
ORDER PART NUMBER LTC693CN LTC693IN LTC693CS LTC693IS
N PACKAGE S PACKAGE 16-LEAD PLASTIC DIP 16-LEAD PLASTIC SOL
TJMAX = 110C, JA = 130C/W (N, S) S16 Package Conditions: PCB Mount on FR4 Material, Still Air at 25C, Copper Trace
LTC692/LTC693
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, TA = 25C, unless otherwise noted.
PARAMETER Battery Backup Switching Operating Voltage Range VCC VBATT VOUT Output Voltage IOUT = 1mA
q
CONDITONS
MIN
TYP
MAX
UNITS
4.50 2.00 VCC - 0.05 VCC - 0.10 VCC - 0.50 VBATT - 0.1
q
5.50 4.00 VCC - 0.005 VCC - 0.005 VCC - 0.250 VBATT - 0.02 0.6 0.6 0.04 0.04 1.5 2.5 1 5 0.02 0.10 70 50 20 0.4
V V V V V V mA mA A A A A mV mV mV V mA A V mV ms ms sec sec ms ms Clock Cycles ms/V ms/V ns
IOUT = 50mA VOUT in Battery Backup Mode Supply Current (Exclude IOUT) Supply Current in Battery Backup Mode Battery Standby Current (+ = Discharge, - = Charge) Battery Switchover Threshold VCC - VBATT Battery Switchover Hysteresis BATT ON Output Voltage (Note 4) BATT ON Output Short-Circuit Current (Note 4) Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis Reset Active Time (Note 5) Watchdog Time-Out Period, Internal Oscillator OSC SEL HIGH, VCC = 5V
q q
IOUT = 250A, VCC < VBATT IOUT 50mA VCC = 0V, VBATT = 2.8V
q
5.5 > VCC > VBATT + 0.2V
q
- 0.1 - 1.0
Power Up Power Down ISINK = 3.2mA BATT ON = VOUT Sink Current BATT ON = 0V Source Current 0.5 4.25 160 140 1.2 1.0 80 70 4032 960
35 1 4.40 40 200 200 1.6 1.6 100 100
25 4.50 240 280 2.00 2.25 120 140 4097 1025
Long Period, VCC = 5V
q
Short Period, VCC = 5V
q
Watchdog Time-Out Period, External Clock (Note 6) Reset Active Time PSRR Watchdog Time-Out Period PSRR, Internal OSC Minimum WDI Input Pulse Width RESET Output Voltage At VCC = 1V RESET and LOW LINE Output Voltage (Note 4) RESET and WDO Output Voltage (Note 4)
Long Period Short Period
1 1 VIL = 0.4V, VIH = 3.5V ISINK = 10A, VCC = 1V ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1A, VCC = 5V ISINK = 1.6mA, VCC = 5V ISOURCE = 1A, VCC = 4.25V 3.5 0.4 3.5
q
200 4 200 0.4
mV V V V V
3
LTC692/LTC693
ELECTRICAL CHARACTERISTICS
VCC = Full Operating Range, VBATT = 2.8V, TA = 25C, unless otherwise noted.
PARAMETER RESET, RESET, WDO, LOW LINE Output Short-Circuit Current (Note 4) WDI Input Threshold WDI Input Current Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR PFI Input Current PFO Output Voltage (Note 4) PFO Short Circuit Source Current (Note 4) PFI Comparator Response Time (falling) PFI Comparator Response Time (rising) (Note 4) Chip Enable Gating CE IN Threshold CE IN Pullup Current (Note 7) CE OUT Output Voltage ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1A, VCC = 0V VCC = 5V, CL = 20pF
q
CONDITONS Output Source Current Output Sink Current Logic Low Logic High WDI = VOUT WDI = 0V VCC = 5V
q q
MIN 1
TYP 3 25
MAX 25 0.8
UNITS A mA V V A A V mV/V nA V V A mA s s s
3.5 - 50 1.25 4 -8 1.3 0.3 0.01 25 0.4 3.5 1 3 25 2 40 8 0.8 2.0 3 0.4 VOUT - 1.50 VOUT - 0.05 20 20 30 35 2 5 35 45 25 50
q
1.35
ISINK = 3.2mA ISOURCE = 1A PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT VIN = -20mV, VOD = 15mV VIN = 20mV, VOD = 15mV with 10k Pull-Up VIL VIH
V V A V V V ns ns mA mA A A
CE Propagation Delay CE OUT Output Short Circuit Current Oscillator OSC IN Input Current (Note 7) OSC SEL Input Pull-Up Current (Note 7) OSC IN Frequency Range OSC IN Frequency with External Capacitor
Output Source Current Output Sink Current
OSC SEL = 0V OSC SEL = 0V, COSC = 47pF
q
0 4
250
kHz kHz
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pull-ups of typically 3A. However, external pull-up resistors may be used when higher speed is required.
Note 5: The LTC692/LTC693 have minimum reset active times of 140ms (200ms typically). The reset active time of the LTC693 can be adjusted (see Table 2 in Applications Information Section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See BLOCK DIAGRAM). Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are floating.
4
LTC692/LTC693
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT vs IOUT
5.00 VCC = 5V VBATT = 2.8V TA = 25C
2.80 VCC = 0V VBATT = 2.8V TA = 25C
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.78 SLOPE = 125 2.76
PFI INPUT THRESHOLD (V)
4.95 4.90 SLOPE = 5 4.85
4.80
4.75
0
10
30 40 20 LOAD CURRENT (mA)
LTC692/3 * TPC01
Reset Active Time vs Temperature
232 VCC = 5V 224 RESET ACTIVE TIME 216 208 200 192 184 -50 -25
4.41
PFO OUTPUT VOLTAGE (V)
RESET VOLTAGE THRESHOLD (V)
50 25 75 0 TEMPERATURE (C)
LTC692/3 * TPC04
Power Fail Comparator Response Time
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
6 5 4 3 2 1 0
VPFI 1.3V + - PFO 30pF
VCC = 5V TA = 25C
1.315V 1.295V 0
VPFI = 20mV STEP
20 40
UW
50
VOUT vs IOUT
1.308 1.306 1.304 1.302 1.300 1.298 1.296 2.72
Power Failure Input Threshold vs Temperature
VCC = 5V
2.74
0
100
300 400 200 LOAD CURRENT (A)
500
1.294 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
LTC692/3 * TPC02
LTC692/3 * TPC03
Reset Voltage Threshold vs Temperature
6 5 4 3 2 1 0
Power Fail Comparator Response Time
VCC = 5V TA = 25C
VPFI 1.3V + - PFO 30pF
4.40 4.39 4.38 4.37 4.36 4.35 -50 -25
1.305V 1.285V
VPFI = 20mV STEP
100
125
50 25 75 0 TEMPERATURE (C)
100
125
0
1
2
345 TIME (s)
6
7
8
LTC692/3 * TPC05
LTC692/3 * TPC06
Power Fail Comparator Response Time with Pull-Up Resistor
6 5 4 3 2 1 0
5V VPFI 1.3V + - PFO 10k 30pF
VCC = 5V TA = 25C
1.315V 1.295V 0 2
VPFI = 20mV STEP
60 80 100 120 140 160 180 TIME (s)
LTC692/3 * TPC07
4
6
8 10 12 14 16 18 TIME (s)
LTC692/3 * TPC08
5
LTC692/LTC693
PI FU CTIO S
VCC: 5V Supply Input. The VCC pin should be bypassed with a 0.1F capacitor. VOUT: Voltage Output for Backed Up Memory. Bypass with a capacitor of 0.1F or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical ON resistance of 5. When VCC is lower than VBATT, VOUT is internally switched to VBATT. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Backup Battery Input. When VCC falls below VBATT, auxiliary power connected to VBATT, is delivered to VOUT through PMOS switch, M2. If backup battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground Pin. BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. RESET: Logic Output for P Reset Control. Whenever VCC falls below either the reset voltage threshold (4.40V typically) or VBATT, RESET goes active low. After VCC returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 140ms. When the watchdog timer is enabled but not serviced prior to a preset time-out period, reset pulse generator also forces RESET to active low for a minimum of 140ms for every preset time-out period (see Figure 11). The reset active time is adjustable on the LTC693. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in the Applications Information section. RESET: RESET is an Active High Logic Ouput. It is the inverse of RESET. LOW LINE: Logic Output from Comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.40V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1). WDI: Watchdog Input. WDI is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 5 for additional information. CE OUT: Logic Output on the Chip Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5). OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low allows OSC IN to be driven from an external clock signal or an external capacitor to be connected between OSC IN and GND.
6
U
U
U
LTC692/LTC693
PI FU CTIO S
OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases the time-out period immediately after a reset is 1.6 seconds typical.
BLOCK DIAGRA
VBATT VCC
CE IN - C3 PFI OSC IN OSC OSC SEL + PFO RESET RESET PULSE GENERATOR RESET WATCHDOG TIMER WDO
LTC692/3 * BD
WDI
W
U
U
U
M2 M1
VOUT
CHARGE PUMP - C2 + LOW LINE + C1 - 1.3V BATT ON
CE OUT
GND
TRANSITION DETECTOR
7
LTC692/LTC693
APPLICATI S I FOR ATIO U
Battery Switchover The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a charge pumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20s. During normal operation, the LTC692/LTC693 use a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical "on" resistance of 5. The VOUT pin should be bypassed with a capacitor of 0.1F or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC - VOUT voltage differential) is desired, the LTC693 should be used. This product provides BATT ON output to drive the base of the external PNP transistor (Figure 2). If higher currents are needed with the LTC692, a high current Schottky diode can be connected from the VCC pin to the VOUT pin to supply the extra current.
V1 V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 t1 t1 = RESET ACTIVE TIME
LTC692/3 * F01
Microprocessor Reset The LTC692/LTC693 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 4.50V (4.40V typical). On power-up, the RESET signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC693. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at the VCC pin do not activate the RESET output. Response time is typically 10s. To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1F capacitor with the leads trimmed as short as possible. The LTC693 has two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold.
V2 VCC
RESET
t1
LOW LINE
8
W
U
UO
Figure 1. Reset Active Time
LTC692/LTC693
APPLICATI
S I FOR ATIO
5
ANY PNP POWER TRANSISTOR
5V 0.1F
3
BATT ON 2 VOUT VCC LTC693 0.1F
1 3V
VBATT GND 4
LTC692/3 * F02
Figure 2. Using BATT ON to Drive External PNP Transistor
The LTC692/LTC693 are protected for safe area operation with a short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long periods of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155C with about 10C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC692/LTC693 use a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by the VBATT pin is strictly junction leakage. A 125 PMOS switch connects the VBATT input to VOUT in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is 1A maximum. The operating voltage at the VBATT pin ranges from 2.0V to 4.0V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term
U
I= VOUT - VBATT R R 5V 0.1F VCC VOUT 0.1F LTC692 LTC693 VBATT 3V GND
LTC692/3 * F03
W
U
UO
Figure 3. Charging External Battery Through VOUT
memory backup instead of a battery. The charging resistor for the rechargeable batteries should be connected to VOUT since this eliminates the discharge path that exists when the resistor is connected to VCC (Figure 3). Replacing the Backup Battery When changing the backup battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC692/LTC693 switch to battery backup. VOUT pulls VBATT low and the devices go back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1A maximum over temperature and the external resistor required to hold VBATT below VCC is:
V - 50mV R CC 1A
With VCC = 4.25V, a 3.9M resistor will work. With a 3V battery, this resistor will draw only 0.77A from the battery, which is negligible in most cases.
9
LTC692/LTC693
APPLICATI S I FOR ATIO U
alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor's address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC692 by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL VCC VOUT VBATT BATT ON PFI PFO RESET RESET STATUS C2 monitors VCC for active switchover. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1A maximum. Logic high. The open-circuit output voltage is equal to VOUT. Power Failure Input is ignored. Logic low Logic low Logic high. The open-circuit output voltage is equal to VOUT. LOW LINE Logic low WDI Watchdog Input is ignored. WDO CE IN CE OUT OSC IN OSC SEL Logic high. The open-circuit output voltage is equal to VOUT. Chip Enable Input is ignored. Logic high. The open-circuit output voltage is equal to VOUT. OSC IN is ignored. OSC SEL is ignored.
V2 V1 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS VOUT = VBATT
LTC692/3 * F05
If battery connections are made through long wires, a 10 to 100 series resistor and a 0.1F capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4).
10 VBATT 3.9M 0.1F LTC692 LTC693
Figure 4. 10/0.1F combination eliminates inductive overshoot and prevents spurious resets during battery replacement.
Table 1 shows the state of each pin during battery backup. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Memory Protection The LTC693 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an
VCC
CE IN
CE OUT VOUT = VBATT
10
W
U
UO
GND
LTC692/3 * F04
Figure 5. Timing Diagram for CE IN and CE OUT
LTC692/LTC693
APPLICATI
5V 0.1F VCC
S I FOR ATIO
+
10F 0.1F
VOUT
LTC693 CE OUT VBATT CE IN RESET RESET
20ns PROPAGATION DELAY FROM DECODER
3V GND
TO P
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V 0.1F
VCC
VOUT
+
10F
0.1F CS
LTC692 VBATT 3V RESET GND
Figure 7. Write Protect for RAM with the LTC692
VIN 7.5V
+
10F R1 51k
LT1086-5 VOUT VIN ADJ
5V
+
VCC LTC692 LTC693 PFO PFI GND
100F R3 300k
0.1F R4 10k
R2 10k
TO P
LTC692/3 * F08
Figure 8. Monitoring Unregulated DC Supply with the LTC692/LTC693 Power Fail Comparator
VIN 6.5V
+
LT1086-5 VIN VOUT ADJ
5V
10F
+
VCC 0.1F LTC692 LTC693 PFO PFI GND TO P
10F
R1 R4 27k 10k R3 2.7M
R2 8.2k R5 3.3k
Figure 9. Monitoring Regulated DC Supply with the LTC692/LTC693 Power Fail Comparator
U
VCC 62512 RAM CS GND
LTC692/3 * F06
W
U
UO
VCC 62128 RAM CS1 CS2 GND
Power Fail Warning The LTC692/LTC693 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V, several milliseconds before the 5V supply falls below the maximum reset voltage threshold of 4.50V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET. The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin. R1 R1 VH = 1.3V 1+ + R2 R3 When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction. R1 (5V - 1.3V)R1 VL = 1.3V 1 + - R2 1.3V(R3 + R4)
LTC692/3 * F07
Assuming R4 << R3,VHYSTERESIS = 5V
R1 R3
LTC692/3 * F09
Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also, the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.25V which is 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.5V + 1.5V) and VHYSTERESIS = 850mV.
11
LTC692/LTC693
APPLICATI
S I FOR ATIO
R1 VHYSTERESIS = 5V = 850mV R3
R3 5.88 R1 Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3. 51k (5V - 1.3V)51k 7.25V = 1.3V 1+ - 1.3 V(310 k ) R2 R2 = 10.1k, Choose nearest 5% resistor 10k and recalculate VL, 51k (5V - 1.3V)51k VL = 1.3V 1 + - = 7.32 V 1.3V(310k ) 10k 51k 51k VH = 1.3V 1 + + = 8.151V 10k 300k
(7.32V - 6.25V) = 10.7ms 100mV/ms
3V
VHYSTERESIS = 8.151V - 7.32V = 831mV The 10.7ms allows enough time to execute shutdown procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN. Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.6V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.
12
U
5V VCC PFO LTC693 LOW BATTERY SIGNAL TO P I/O PIN VBATT R1 1M PFI R2 1M CE OUT RL 20K OPTIONAL TEST LOAD
LTC692/3 * F10
W
U
UO
CE IN GND
I/O PIN
Figure 10. Backup Battery Monitor with Optional Test Load
Watchdog Timer The LTC692/LTC693 provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 140ms. The reset active time is adjustable on the LTC693. Since many systems cannot service the watchdog timer immediately after a reset, the LTC693 has longer time-out period (1.0 second minimum) right after a reset is issued. The normal time-out period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at a 1.0 second minimum on the LTC692. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog timer is reset and begins to time-out again. To ensure the watchdog timer does not time-out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT.
LTC692/LTC693
APPLICATI S I FOR ATIO U
GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 140ms minimum. OSC IN selects between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second.
t1 = RESET ACTIVE TIME t2 = NORMAL WATCHDOG TIME-OUT PERIOD t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A RESET t3 t1
LTC692/3 * F11
The LTC693 provides an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT. The LTC693 has two additonal pins OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and
VCC = 5V WDI
WDO
RESET t1
Figure 11. Watchdog Time-out Period and Reset Active Time
EXTERNAL CLOCK 5V 3 VCC OSC SEL 8 5V 3 EXTERNAL OSCILLATOR VCC OSC SEL 8
LTC693 4 GND OSC IN 7 4
INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG 5V 3 VCC OSC SEL 8 FLOATING OR HIGH 5V 3
LTC693 4 7 FLOATING OR HIGH 4
GND
W
U
UO
t2
LTC693
GND
OSC IN
7
INTERNAL OSCILLATOR 100ms WATCHDOG VCC OSC SEL 8 FLOATING OR HIGH
LTC693 7
OSC IN
GND
OSC IN
Figure 12. Oscillator Configurations
LTC692/3 * F12
13
LTC692/LTC693
APPLICATI
S I FOR ATIO
Table 2. LTC693 Reset Active Time and Watchdog Time-Out Selections
WATCHDOG TIME-OUT PERIOD OSC SEL OSC IN NORMAL (Short Period) Low Low Floating or High Floating or High External Clock Input External Capacitor* Low Floating or High 1024 clks 400ms xC 47pF 100ms 1.6 sec IMMEDIATELY AFTER RESET (Long Period) 4096 clks 1.6 sec xC 47pF 1.6 sec 1.6 sec 184,000 C(pF) RESET ACTIVE TIME
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is FOSC (Hz) =
Pushbutton Reset The LTC692/LTC693 do not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 100 resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1F capacitor to the RESET pin debounces the pushbutton input. The 100 resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC692/LT693 below ground.
5V VCC RESET LTC692 LTC693 GND 0.1F 100 RESET MPU (e.g. 6805)
TYPICAL APPLICATI
S
Capacitor Backup with 74HC4016 Switch
R1 10k 1 R2 30k
10 11 12 14 74HC4016 7 13 2 VBATT
14
U
LTC693 2048 clks 800ms xC 47pF 200ms 200ms
LTC692/3 * F13
W
UO
U
UO
Figure 13. The External Pushbutton Reset
5V VCC 0.1F LTC693 LOW LINE VOUT 0.1F
+
100F
GND
LTC692/3 * TA3
LTC692/LTC693
TYPICAL APPLICATI
5V 0.1F
3V
PACKAGE DESCRIPTIO
0.300 - 0.320 (7.620 - 8.128)
N8 Package 8-Lead Plastic DIP
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.010 - 0.020 x 45 (0.254 - 0.508)
S8 Package 8-Lead Plastic SOIC
0.008 - 0.010 (0.203 - 0.254) 0.016 - 0.050 0.406 - 1.270
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
U
UO
S
Write Protect for Additional RAMs
0.1F VCC LTC693 CE OUT VBATT CE IN LOW LINE GND 0.1F VCC 62128 RAMB CS1 CS2 0.1F VCC 62128 RAMC CSC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs
LTC692/3 * TA04
VOUT
+
10F
VCC 62512 RAMA CS
20ns PROPAGATION DELAY CSA
CSB
Dimensions in inches (millimeters) unless otherwise noted.
0.400 (10.160) MAX 8 7 6 5
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN
0.250 0.010 (6.350 0.254)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
1
2
3
4
N8 0393
0.018 0.003 (0.457 0.076)
0.189 - 0.197 (4.801 - 5.004) 0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157 (3.810 - 3.988) 8 7 6 5
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
SO8 0393
1
2
3
4
15
LTC692/LTC693
PACKAGE DESCRIPTIO
0.300 - 0.325 (7.620 - 8.255)
0.130 0.005 (3.302 0.127)
0.009 - 0.015 (0.229 - 0.381)
0.015 (0.381) MIN
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.125 (3.175) MIN
0.100 0.010 (2.540 0.254)
0.005 (0.127) RAD MIN
0.291 - 0.299 (7.391 - 7.595) (NOTE 2) 0.010 - 0.029 x 45 (0.254 - 0.737)
0 - 8 TYP 0.050 (1.270) TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
U
Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead Plastic DIP
0.770 (19.558) MAX 16 15 14 13 12 11 10 9
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP
0.260 0.010 (6.604 0.254)
1 0.045 0.015 (1.143 0.381) 0.018 0.003 (0.457 0.076)
2
3
4
5
6
7
8
N16 0393
S Package 16-Lead SOL
0.398 - 0.413 (10.109 - 10.490) (NOTE 2) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143) 16 15 14 13 12 11 10 9
0.004 - 0.012 (0.102 - 0.305)
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
0.014 - 0.019 (0.356 - 0.482) TYP
1
2
3
4
5
6
7
8
S16 0393
LT/GP 0493 10K REV 0
(c) LINEAR TECHNOLOGY CORPORATION 1993

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